This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution).
addr/data: 8 8
0
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-- HEIG-VD, institute REDS, 1400 Yverdon-les-Bains
-- Project :
-- File :
-- Autor :
-- Date :
--
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-- Description :
--
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library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
entity VHDL_Component is
port(
------------------------------------------------------------------------------
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
------------------------------------------------------------------------------
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end VHDL_Component;
--------------------------------------------------------------------------------
--Complete your VHDL description below
architecture type_architecture of VHDL_Component is
begin
end type_architecture;
library ieee;
use ieee.std_logic_1164.all;
entity TCL_Generic is
port(
--Insert input ports below
horloge_i : in std_logic; -- input bit example
val_i : in std_logic_vector(3 downto 0); -- input vector example
--Insert output ports below
max_o : out std_logic; -- output bit example
cpt_o : out std_logic_Vector(3 downto 0) -- output vector example
);
end TCL_Generic;
addr/data: 11 8
40 14 6*0 40 14 48 12 4*0
40 14 48 10 2 0 0 0
40 14 48 10 2 0 0 0
40 14 48 21 4*0 40 14 a
5*0 40 14 8 5*0 40 14 6*0
40 14 6*0 40 14 6*0 40 14
6*0 40 14 6*0 40 14 6*0 40
14 6*0 40 14 1 5*0 40 14
80 5*0 40 14 6*0 40 14 48
12 4*0 40 14 48 10 2 0
0 0 40 14 48 10 2 0
0 0 40 14 48 21 4*0 40
14 a 5*0 40 14 8 5*0 40
14 8 5*0 40 14 6*0 40 14
6*0 40 14 6*0 40 14 6*0 40
14 6*0 40 14 6*0 40 14 1
5*0 40 14 80 5*0 40 14 6*0
40 14 48 12 4*0 40 14 48
10 2 0 0 0 40 14 48
10 2 0 0 0 40 14 48
21 4*0 40 14 a 5*0 40 14
8 5*0 40 14 6*0 40 14 8
5*0 40 14 6*0 40 14 6*0 40
14 6*0 40 14 6*0 40 14 6*0
40 14 1 5*0 40 14 80 5*0
40 14 6*0 40 14 48 12 4*0
40 14 48 10 2 0 0 0
40 14 48 10 2 0 0 0
40 14 48 21 4*0 40 14 a
5*0 40 14 8 5*0 40 14 8
5*0 40 14 8 5*0 40 14 6*0
40 14 6*0 40 14 6*0 40 14
6*0 40 14 6*0 40 14 1 5*0
40 14 80
addr/data: 11 8
4 8 6*0 4 8 6*0 4 8
0 20 81 0 0 0 4 8
0 20 c1 0 0 0 4 8
6*0 4 8 6*0 4 8 2 5*0
4 8 6*0 4 8 6*0 4 8
6*0 4 8 6*0 4 8 6*0 4
8 6*0 4 8 6*0 4 8 10
5*0 4 8 6*0 4 8 6*0 4
8 6*0 4 8 0 20 81 0
0 0 4 8 0 20 c1 0
0 0 4 8 6*0 4 8 6*0
4 8 2 5*0 4 8 2 5*0
4 8 6*0 4 8 6*0 4 8
6*0 4 8 6*0 4 8 6*0 4
8 6*0 4 8 10 5*0 4 8
6*0 4 8 6*0 4 8 6*0 4
8 0 20 81 0 0 0 4
8 0 20 c1 0 0 0 4
8 6*0 4 8 6*0 4 8 2
5*0 4 8 6*0 4 8 2 5*0
4 8 6*0 4 8 6*0 4 8
6*0 4 8 6*0 4 8 6*0 4
8 10 5*0 4 8 6*0 4 8
6*0 4 8 6*0 4 8 0 20
81 0 0 0 4 8 0 20
c1 0 0 0 4 8 6*0 4
8 6*0 4 8 2 5*0 4 8
2 5*0 4 8 2 5*0 4 8
6*0 4 8 6*0 4 8 6*0 4
8 6*0 4 8 6*0 4 8 10
5*0 4 8
INC_ENABLE
STEP
ADDR
DATA
RESET
addr/data: 4 8
0
BCD_IN
SEG_OUT
addr/data: 4 7
7e 30 6d 79 33 5b 5f 70
7f 7b
BYTE_IN
SEG_0
SEG_1
SEG_2
addr/data: 8 12
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255